Dedication	6
	Preface	8
	Contents	12
	Abbreviations	16
	Chapter 1: Introduction	18
	1.1 The AMS IC Design Flow	18
	1.2 Motivation for Analog Design Automation	21
	1.3 Analog Layout Automation	23
	1.4 Advances to the State-of-the-Art	25
	1.5 Conclusion	26
	References	27
	Chapter 2: State-of-the-Art on Analog Layout Automation	28
	2.1 Placement	29
	2.1.1 Analog Topological Constraints	29
	2.1.2 Floorplan Representations	30
	2.1.2.1 Absolute Representation	30
	2.1.2.2 Relative Representation	31
	Slicing	31
	Non-slicing	32
	2.1.3 Challenges in Modern Analog Placement	34
	2.1.3.1 Pareto Front of Placement Solutions	34
	2.1.3.2 Thermal-Driven Placement	36
	2.1.3.3 Current-Driven Placement	36
	2.1.4 Optimization Algorithm of Choice: Simulated Annealing	37
	2.1.5 Commercial Solutions	37
	2.2 Routing	38
	2.2.1 From Netlist to Pathfinding	38
	2.2.2 Electromigration and IR-Drop	39
	2.2.3 Electromigration-Aware Approaches	40
	2.2.4 Wiring Symmetry	41
	2.2.5 Commercial Solutions	41
	2.3 Complete Layout Generation Tools	42
	2.3.1 Procedural Generation	42
	2.3.2 Template-Based	42
	2.3.3 Optimization-Based	43
	2.3.4 Commercial Solutions	44
	2.4 Closing the Gap Between Electrical and Physical Design	46
	2.4.1 Circuit Sizing Task	47
	2.4.2 Layout Generators Embedded in Layout-Aware Approaches	47
	2.4.3 Parasitic Extractors Used in Layout-Aware Approaches	48
	2.5 Overview of the State-of-the-Art on Analog Layout Automation	49
	2.5.1 Support User-Assisted Placement Generation	49
	2.5.2 Support Fully-Automatic Placement Generation	51
	2.5.3 Alleviate Designer from the Routing Task	52
	2.5.4 Embedding in a Layout-Aware Circuit Sizing Methodology	52
	2.6 Conclusions	53
	References	53
	Chapter 3: AIDA-L: Architecture and Integration	59
	3.1 Standalone Design Flow	59
	3.1.1 User-Assisted Floorplan Generation	60
	3.1.2 Fully-Automatic Floorplan Generation	62
	3.2 Standalone Design Flow	63
	3.2.1 Inputs	64
	3.2.1.1 Template-Based Placer: Hierarchical High Level Floorplan and Devices’ Sizes	64
	3.2.1.2 Optimization-Based Placer: Topological Constraints, Devices’ Sizes, Current-Flows and Electric-Current Values	65
	3.2.1.3 Router: Netlist and Electric-Current Values	65
	3.2.2 Outputs	67
	3.2.3 Technology Design Kit and AIDA-AMG	67
	3.2.4 Graphical User Interface	68
	3.2.5 Automatic Layout Generation Using AIDA-L	69
	3.3 Integration on AIDA’s Framework	70
	3.3.1 Layout-Aware Design Flow	71
	3.3.2 Floorplan-Aware Loop	72
	3.3.3 Parasitic-Aware Loop	73
	3.4 Conclusion	74
	References	75
	Chapter 4: Template-Based Placer	76
	4.1 Template-Based Placer Architecture	76
	4.2 XML Description for Template-Based Placement	78
	4.2.1 Automatic Generation from the Netlist	78
	4.2.2 Designer Guidelines	80
	4.3 B*-Tree Extraction	83
	4.4 Instantiation: AIDA’s Analog Module Generator	84
	4.4.1 Supported Structures	86
	4.4.2 Biasing	88
	4.4.3 Handling of Complex Layout Structures	89
	4.4.4 Multiport Terminals	89
	4.5 B*-Tree Packing	91
	4.6 Case Study: Simple Differential Amplifier	91
	4.6.1 Floorplan Generation: Design 1	92
	4.6.2 Retargeting Operation: Design 2	93
	4.6.3 Retargeting Operation: Design 3	94
	4.7 Conclusion	95
	References	96
	Chapter 5: Optimization-Based Placer	97
	5.1 Optimization-Based Placer Architecture	98
	5.2 Constrained Archive-Based Multi-Objective Simulated Annealing Algorithm	99
	Dominance Measures	101
	5.2.1 Double Annealing Schedule	102
	5.2.2 Archive Compaction	103
	5.3 XML Description for Optimization-Based Placement	103
	5.4 Hierarchical Placement Optimization in Absolute Coordinates	104
	5.4.1 Analog Constraints and Proximity Groups	104
	5.4.2 Absolute Coordinates’ Problem Definition	108
	5.4.3 Multi-Objective Hierarchical Framework	109
	5.5 Current-Flow and Current-Density Considerations	110
	5.5.1 Current-Flow Constraints	110
	5.5.2 Current-Density Considerations	113
	5.5.3 Application in the Hierarchical Framework	114
	5.6 Conclusion	115
	References	117
	Chapter 6: Fully-Automatic Router	119
	6.1 Router Architecture	119
	6.1.1 Evolution of AIDA-L’s Routing Paradigm	120
	6.1.2 Current Architecture/Design Flow	120
	6.2 Electromigration-Aware Wiring Planner	123
	6.2.1 Electromigration and IR-Drop-Reliable Interconnects’ Widths	124
	6.2.2 Problem Formulation	125
	6.2.3 Optimal Wire Planning	127
	6.2.3.1 Network Graph	127
	6.2.3.2 Residual Network	128
	6.2.3.3 Negative Cycle Cancelling	129
	6.2.4 Strongly Connected Network	130
	6.3 Symmetry Planner	131
	6.3.1 Symmetry Extraction	131
	6.3.2 Wire Symmetry Analysis	132
	6.4 Global Router: Step I—Multilayer Multiport Selection	134
	6.4.1 Multiport Multiterminal Signal Nets	134
	6.4.2 Multilayer Multiport Obstacle-Aware Grid	135
	6.4.3 Multiport Selection	137
	6.4.4 Wiring Symmetry in the Pathfinding Algorithm	139
	6.5 Global Router: Step II—Steiner Point Assignment	140
	6.5.1 Basic Assignment	140
	6.5.2 Assignment over Obstacles	141
	6.5.3 Symmetry Considerations	141
	6.6 Detailed Router	144
	6.6.1 Evolutionary Algorithm	145
	6.6.2 Chromosome Structure	146
	6.6.3 Optimization Phases	147
	6.7 Conclusion	148
	References	149
	Chapter 7: Empirical-Based Parasitic Extractor	151
	7.1 Empirical-Based Parasitic Extractor Architecture	151
	7.2 Intercap Models Processing	152
	7.3 RC Extraction	154
	7.3.1 Parasitic Resistance	157
	7.3.2 Parasitic Capacitances	158
	7.3.2.1 Substrate Capacitance	159
	7.3.2.2 Lateral Capacitance	159
	7.3.2.3 2.5-D Capacitance	160
	7.3.3 Geometrical Considerations	161
	7.4 Case Study: Single Ended Two-Stage Amplifier	161
	7.5 Conclusion	168
	References	169
	Chapter 8: Experimental Results	170
	8.1 Organization of the Results	170
	8.2 Case Study I: Single Stage Amplifier with Gain Enhancement Using Voltage Combiner	172
	8.2.1 Inputs: Template File Definition and Floorplan-Aware Circuit Sizing	172
	8.2.2 Layout Generation: Template-Based Placer	174
	8.2.3 Layout Generation: Optimization-Based Placer with Current-Flow and Current-Density Considerations	177
	8.3 Case Study II: Single Ended Two-Stage Amplifier	180
	8.3.1 Inputs: Template File Definition and Floorplan-Aware Circuit Sizing	180
	8.3.2 Layout Generation: Template-Based Placer	183
	8.3.3 Parasitic Extraction and Layout-Aware Circuit Sizing	186
	8.4 Case Study III: Two-Stage Folded Cascode Amplifier	188
	8.4.1 Parasitic Extraction and Layout-Aware Circuit Sizing	188
	8.4.2 Layout Generation: Optimization-Based Placer	192
	8.4.3 Layout Generation: Optimization-Based Placer with Current-Flow and Current-Density Considerations	194
	8.5 Case Study IV: Operational Transconductance Amplifier	196
	8.6 Benchmarks	200
	8.6.1 Optimization-Based Placer Benchmark: Single-Objective vs. Multi-Objective	200
	8.6.2 MCNC Benchmarks: Optimization-Based Placer vs. Topological	203
	8.6.3 Routing Benchmark: Single-Port vs. Multiport	205
	8.7 Conclusion	205
	References	211
	Chapter 9: Conclusions and Future Work	212
	9.1 Conclusions	212
	9.2 Future Work	214
	9.2.1 Improved Efficiency	214
	9.2.2 Radio-Frequency	214
	9.2.3 Deep-Nanometer Technologies	215
	Index	216