Preface	8
	Contents	10
	Contributors	12
	Part I Process and Design	14
	1 Overview of the Interconnect Problem	15
	1.1 Overview	15
	1.2 The Interconnect Structure Design Challenge	17
	1.3 Intrinsic Interconnect Parameters	18
	1.3.1 Interconnect Resistance	18
	1.3.2 Interconnect Capacitance	20
	1.4 Impact on Interconnect Metrics	22
	1.5 Impact at the Circuit Level	25
	1.5.1 Physical Design of Circuit Blocks at Future Technology Generations	27
	1.5.1.1 Interconnect and Standard Cell Definitions	28
	1.5.1.2 Experiment Setup and Results	31
	1.5.1.3 Critical Path Delay	31
	1.5.1.4 Power Dissipation	33
	1.5.2 Impact of Vias	34
	1.6 Impact at the Full-chip Level	36
	1.6.1 System Modeling Based on Wirelength Distribution	37
	1.6.1.1 Resistivity Impact on the Number of Metal Levels	39
	1.6.1.2 Barrier Thickness Impact on the Number of Metal Levels	41
	1.6.1.3 Interconnect Variability Impact on the Number of Metal Levels	42
	1.7 Reliability Challenges	43
	1.7.1 Cu Electromigration	44
	1.7.2 Time-Dependent Dielectric Breakdown	44
	1.8 Conclusion and Outlook	45
	References	46
	2 Overview of Carbon Nanotube Interconnects	49
	2.1 Introduction	49
	2.2 Carbon Nanotubes and Graphene Nanoribbon Interconnects	51
	2.2.1 CNTs Interconnects	51
	2.2.2 Graphene Nanoribbon Interconnects	52
	2.3 Challenges for CNT-Based and Graphene Nanoribbon Interconnects	53
	2.3.1 Challenges for CNT-Based Interconnects	53
	2.3.1.1 High Density Synthesis of CNTs-Based Via Interconnects	54
	2.3.1.2 Low Temperature Synthesis of CNT-Based Via Interconnects	57
	2.3.1.3 CNT-Based Horizontal Interconnects	60
	2.3.1.4 A High Quality Contact of CNT-Metal	62
	2.3.1.5 Selective Growth of Metallic CNTs	65
	2.3.1.6 CNTs-Based Through-Silicon-Via for 3D Integration	67
	2.3.2 The Challenges for Graphene Nanoribbon Interconnects	69
	2.3.2.1 Graphene Fabrication	69
	2.3.2.2 Fabrication of Graphene Nanoribbon Interconnects	70
	2.3.2.3 Multi-Layer GNR Interconnects	71
	2.3.2.4 Performance and Reliability of GNR Interconnects	73
	2.3.2.5 GNR Interconnects in All-Graphene Circuits	75
	2.4 Conclusion	77
	References	77
	3 Overview of Carbon Nanotube Processing Methods	93
	3.1 Introduction	93
	3.2 Growth of Carbon Nanotubes	94
	3.3 Chemical Vapor Deposition Growth	97
	3.4 Vertical Alignment of Carbon Nanotubes	98
	3.5 Hidden Growth Parameter	100
	3.6 Horizontal Alignment of Carbon Nanotubes	102
	3.7 Carbon Nanotubes: Copper Composite Interconnects	104
	3.8 Macroscopic Carbon Nanotube Interconnects: Cables and Wires	106
	3.9 Outlook	110
	References	111
	4 Electrical Conductivity of Carbon Nanotubes: Modeling and Characterization	113
	4.1 Introduction	113
	4.2 Band Structure of Carbon Nanotubes and Energy Subbands	114
	4.3 Electrical Conductivity of Isolated CNTs, from DC to THz Range	116
	4.3.1 Transport Equation	116
	4.3.2 Equivalent Parameters for an Isolated CNT	121
	4.3.3 Plasmon Resonances in CNTs	123
	4.4 Equivalent Resistivity for a CNT Bundle from DC to THz	127
	4.4.1 A Bundle of CNTs Without Intershell Coupling	127
	4.4.2 A Bundle of CNTs in Presence of Intershell Coupling	130
	4.5 Electrical Conductivity of CNTs up to the Optical Range	134
	4.6 Conclusions	138
	References	138
	5 Computational Studies of Thermal Transport Properties of Carbon Nanotube Materials	141
	5.1 Introduction	141
	5.2 Atomistic Modeling of Thermal Conductivity of Individual CNTs	144
	5.3 Atomistic Modeling of Inter-Tube Contact Conductance	149
	5.4 Mesoscopic Modeling of Thermal Transport in CNT Network Materials	155
	5.5 Derivation of Scaling Laws and Monte Carlo Simulations	161
	5.6 Concluding Remarks	164
	References	166
	Part II Applications	174
	6 Overview of Carbon Nanotubes for Horizontal On-Chip Interconnects	175
	6.1 Introduction	175
	6.2 Brief Theoretical Reminder	176
	6.3 CNT Density in Interconnections	178
	6.4 CNT Integration in Horizontal Lines	181
	6.5 CNT Contacts	185
	6.5.1 End-Bonded Contacts	186
	6.5.2 Side-Bonded Contacts	188
	6.6 Performances of CNT Lines	190
	6.7 Local Interconnects Made of Individual CNTs	194
	6.8 CNT Doping	199
	6.9 Conclusion	199
	References	200
	7 Carbon Nanotubes as Vertical Interconnects for 3D Integrated Circuits	205
	7.1 Introduction	205
	7.2 Requirements for CNT Integration	208
	7.3 CNT for Vertical Interconnects	209
	7.4 Carbon Nanotube TSV	213
	7.5 Towards the Integration of CNT with Monolithic 3D IC	215
	7.6 Conclusion and Future Prospects	218
	References	219
	8 Carbon Nanotubes as Microbumps for 3D Integration	224
	8.1 Introduction	224
	8.1.1 Level 0 of Interconnection Using CNTs	225
	8.1.1.1 Local Interconnections Using CNTs [3]	226
	8.1.1.2 Semi-Global Interconnections Using CNTs	226
	8.1.1.3 Global Interconnections Using CNTs	227
	8.1.1.4 Conclusion	227
	8.1.2 Level 1 of Interconnection Using CNTs [4, 6–8]	228
	8.1.2.1 Wire Bonding	228
	8.1.2.2 Hot-Via [9–11]	229
	8.1.2.3 Flip Chip	229
	8.2 CNT-Based Microbumps	231
	8.2.1 CNT Growth on Gold Metallization	232
	8.2.1.1 Test Structure	232
	8.2.1.2 Results and Discussion	233
	8.2.2 RF Flip Chip Test Structure Based on CNT Bumps	235
	8.2.2.1 Design and Fabrication	235
	8.2.2.2 Fabrication Results	241
	8.2.2.3 DC Measurements: CNT Bump Resistance and Reworkability	243
	8.2.2.4 RF Measurements: Discussion	245
	8.2.2.5 Hybrid (EM/Analytical) Modelling	248
	8.3 Conclusion and Future Work	250
	References	251
	9 Electrothermal Modeling of Carbon Nanotube-Based TSVs	255
	9.1 Introduction	255
	9.2 Temperature-Dependent Thermal Conductivity and Specific Heat of CNTs	257
	9.3 Electrical Properties of CNT-TSVs	261
	9.4 Electrothermal Modeling of a Pair of CNT-TSVs	267
	9.5 Crosstalk Effects in CNT-TSVs	275
	9.6 3-D Carbon-Based Heterogeneous Interconnects	278
	9.7 Conclusion	286
	References	287
	10 Exploring Carbon Nanotubes for 3D Power Delivery Networks	290
	10.1 Introduction	290
	10.2 Modeling of CNTs	291
	10.3 CNTs for 2D Power Delivery Network	294
	10.3.1 Branch Analysis with CNTs	296
	10.4 CNTs for 3D Power Delivery Network	300
	10.4.1 TSV CNT Analysis	304
	10.4.2 Voltage Drop Analysis on a 3D PDN	306
	10.5 Thermal Modeling for CNTs	308
	10.6 Conclusion	318
	References	320
	11 Carbon Nanotubes for Monolithic 3D ICs	322
	11.1 Introduction to Monolithic 3D Integration	323
	11.1.1 Challenges for Monolithic 3D ICs	324
	11.1.2 Enabling Monolithic 3D: CNTs and Emerging Nanotechnologies	324
	11.2 CNFETs for Monolithic 3D ICs	326
	11.2.1 CNTs as a Digital Logic Technology	326
	11.2.2 Overcoming CNT Obstacles	327
	11.2.3 Fabricating Monolithic 3D CNFET ICs	330
	11.3 Experimental Demonstrations	332
	11.3.1 Monolithic 3D CNFET ICs	332
	11.3.2 Hybrid CNFET-Silicon CMOS Monolithic 3D ICs	332
	11.3.3 Monolithic 3D Integration: Logic+Memory	334
	11.4 Outlook: Ongoing and Future Work	335
	References	336